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as1545 dual, 12-bit, 1msps, sar adc www.austriamicrosystems.com revision 1.01 1 - 34 datasheet 1 general description the as1545 is a dual, 12-bit, 6-channel, 1 msps, high speed, successive approximation (sar) analog-to- digital converters (adcs). the as1545 is designed to operate with a single +2.7v to +5.25v supply and a sampling rate of up to 1 msps. the device contains two adcs, each preceded by a 6- channel multiplexer and a high-bandwidth track/hold amplifier. data access is made via standard control inputs in support of wide range of microprocessors and dsps. the device requires very lo w supply-current at the 1msps maximum sampling speed, and features flexible power-down modes to reduce power consumption at slower throughput rate. the as1545 contains an internal 2.5v reference and integrated reference buffer that can be over driven when an external reference is required. superior ac characteristic s, low power consumption, and highly reliable packaging makes the as1545 perfect for portable battery-powered remote sensors and data- acquisition devices. the as1545 is available in a 32-lead tqfn package. figure 1. as1545 - block diagram 2 key features sampling rate: 1msps per adc dual 12-bit serial interface software configurable analog input types: - 12-channel single-ended - 6-channel pseudo-differential - 6-channel fully differential internal +2.5v reference or external: 1v to v dd rail to rail common mode input range low-power consumption - 15mw max. at 1msps with 2.7v supplies - 37mw max. at 1msps with 5.25v supplies dual conversion with read at 20 mhz sclk single-supply operation: +2.7v to +5.25v motor control registers: difference of inputs, quadrature signal phases, direction and step down counter 32-lead tqfn package 3 applications the device is ideal for motor control like encoder feed- back or current sense, moti on control such as robotics, sonar, or for any other ra dio frequency identification. bin 1 bin 2 bin 3 bin 4 bin 5 ain 0 ain 1 ain 2 ain 3 ain 4 ain 5 bin 0 control logic and system control registers 12-bit sar and a/d conversion control ref_select 12-bit sar and a/d conversion control buf buf t/h t/h mux ref mux output drivers output drivers refa avdd dvdd sclk csn range douta sgl/diff a0 a1 a2 vdrive doutb dgnd dgnd refb agnd agnd agnd system control registers as1545
www.austriamicrosystems.com revision 1.01 2 - 34 as1545 datasheet contents 1 general description ............................................................................................................................... ................. 1 2 key features ............................................................................................................................... ............................ 1 3 applications ............................................................................................................................... .............................. 1 4 pinout ............................................................................................................................... ....................................... 3 pin assignment ................................................................................................................ .................................... 3 pin description .............................................................................................................. ...................................... 3 5 absolute maximum ratings ............................................................................................................................... ..... 5 6 electrical characteristics ............................................................................................................................... .......... 6 timing characteristics .................................... .................................................................... ............................. 9 7 typical operating characteristics ......................................................................................................................... 10 8 terminology ............................................................................................................................... ............................ 15 9 detailed description ............................................................................................................................... ............... 18 analog input .................................................................................................................. ..................................... 18 acquisition time .............................................................................................................. .............................. 18 analog input composition ...................................................................................................... ....................... 19 analog input modes ............................................................................................................ .......................... 20 single-ended mode ............................................................................................................. .......................... 21 fully differential mode ....................................................................................................... ........................... 21 pseudo differential mode ...................................................................................................... ........................ 22 analog-to-digital conversion ........ .......................................................................................... ........................... 23 output coding ................................................................................................................. .............................. 23 transfer functions ......................................... ................................................................... ............................ 23 digital inputs ................................................................................................................ ...................................... 24 vdrive functionality........................................................................................................... .......................... 24 10 application information ............................................................................................................................... ........ 25 operation modes ............................................................................................................... ................................ 25 full power-up mode ............................................................................................................ ......................... 25 full power-down mode .......................................................................................................... ....................... 25 partial power-down mo de ....................................................................................................... ..................... 26 power-up times ................................................................................................................ ........................... 27 power vs. throughput rate ..................................................................................................... ..................... 28 serial interface .............................................................................................................. ..................................... 28 difference calculator and quadrature signals calculator ............. .............. ........... ............ ........... .......... ......... 29 direction of the rotor based on di r bit ....................................................................................... ................... 30 11 application hints ............................................................................................................................... ................... 31 grounding and layout ........ .............. .............. .............. .............. .............. .............. .............. ......................... 31 pcb design guidelines for tqfn . ............................................................................................... ................. 31 12 package drawings and markings ........................................................................................................................ 32 13 ordering information ............................................................................................................................... ............ 33
www.austriamicrosystems.com revision 1.01 3 - 34 as1545 datasheet - pinout 4 pinout pin assignment figure 2. pin assignments (top view) pin description table 1. pin description pin number pin name description 1, 29 dgnd digital ground. ground reference point for the digital portion of the as1545. 2 ref_select reference select pin. internal/external reference selection. logic input. if this pin is tied to dgnd, the on-chip 2. 5v reference is used as the reference source for both adc a and adc b. in addition, pin refa and pin refb must be tied to decoupling capacitors. if the ref select pin is tied to a logic high, an external reference can be supplied to the as1545 through the ref a or ref b pins. 3av dd analog supply voltage. 2.7v to 5.25v. 4, 20 ref a , ref b reference input/output. these pins are connected to the internal reference through a series resistor and is the reference source for the as1545. the nominal reference voltage is 2.5v and appears at the pin. this pin can be over-driven by an external reference or can be taken as high as av dd . decoupling capacitors (4.7 uf recommended) are connected to these pins to decouple the reference buffer for each respective adc. 5agnd analog ground. decouple point for av dd . ground reference for track/hold, reference, and dac circuits. 6, 19 agnd analog ground. decouple point for v ref capacitors and analog input filters. pin 6 is the decoupling poin t for refa, pin 19 for refb. ground reference for track/hold, reference, and dac circuits. 7 to 12 ain0 to ain5 analog inputs of adc a. these may be programmed as six single-ended channels, three pseudo-differential or three true-differential analog input channel pairs. as1545 2 a2 1 sclk 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ain 0 ain 1 ain 2 ain 3 ain 4 ain 5 bin 5 bin 4 bin 3 bin 2 bin 1 bin 0 agnd refb range sgl/diff a1 a0 csn doutb dgnd douta vdrive dvdd agnd agnd refa avdd ref_select dgnd 33 exp. pad
www.austriamicrosystems.com revision 1.01 4 - 34 as1545 datasheet - pinout 13 to 18 bin0 to bin5 analog inputs of adc b. these may be programmed as six single-ended channels, three pseudo-differential or three true-differential analog input channel pairs. (see table 5 on page 20) . 21 range analog input range selection. logic input. the polarity on this pin determines the input range of the analog input channels. if this pin is tied to a logic low, the analog input range is 0v to v ref . if this pin is tied to a logic high when csn goes low, the analog input range is 2 v ref . 22 sgl/diff logic input. this pin selects whether the analog inputs are configured as differential pairs or single ended. a logic low selects differential operation while a logic high selects single-ended operation. 23 to 25 a2 to a0 multiplexer select. logic inputs. these inputs are used to select the pair of channels to be simultaneously convert ed, such as channel 1 of both adc a and adc b, channel 2 of both adc a and adc b, and so on. 26 csn chip select. active low logic input. this input provides the dual function of initiating conversions on the as1545 and framing the serial data transfer. 27 sclk serial clock input. a serial clock input provides the sclk for accessing the data from the as1545. this clock is also used as the clock source for the conversion process. 28, 30 d outb , d outa serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input and 15 sclks are required to access the data. the data simultaneously appears on both pins from the simult aneous conversions of both adcs. the data stream consists of three leadin g zeros followed by the 12 bits of conversion data. the data is provided msb first. if csn is held low for 16 sclk cycles rather than 15, then singl e trailing zero appears after the 12bits of data. if csn is held low for a fu rther 16 sclk cycl es on either d outa or d outb , futher data is clocked out according to the timing diagram. 31 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operates. this pin should be decoupled to dgnd. the voltage at this pin may be different than that at av dd and dv dd but should never exceed either by more than 0.3v. 32 dv dd digital supply voltage. 2.7v to 5.25v. this is the supply voltage for all digital circuitry on the as1545. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3v apart even on a transient basis. this supply should be decoupled to dgnd. 33 exp. pad exposed pad. this pin can be not connected or connected agnd. the exposed pad must not be connected to v dd . table 1. pin description pin number pin name description
www.austriamicrosystems.com revision 1.01 5 - 34 as1545 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical characteristics on page 6 is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments v dd to agnd -0.3 +7 v dv dd to dgnd -0.3 +7 v v drive to dgnd -0.3 dv dd v v drive to agnd -0.3 av dd v av dd to dv dd -0.3 +0.3 v agnd to dgnd -0.3 +0.3 v analog input voltage to agnd -0.3 av dd + 0.3 v digital input voltage to dgnd -0.3 +7 v digital output voltage to dgnd -0.3 v drive + 0.3 v refa, refb to agnd -0.3 av dd + 0.3 v input current to all pins except av dd or dv dd 10 ma electro-static discharge 2kv operating temperature range -40 +85 oc storage temperature range -65 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020d ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com revision 1.01 6 - 34 as1545 datasheet - electrical characteristics 6 electrical characteristics av dd = dv dd = 2.7v to 5.25v, v drive = 2.7 v to av dd /dv dd , f sclk = 20 mhz, f sample = 1 msps, t amb = -40 to +85c, external reference = 2.5v, range = 0, typical val ues at 5.25v and 25c with external reference; unless oth - erwise specified. table 3. electrical characteristics symbol parameter condition min typ max unit dynamic specifications 50khz sinewave input sinad signal to noise + distortion ratio fully differential mode 70 72 db snr signal-to-noise ratio 71 72.5 thd total harmonic distortion -81 -77 sfdr spurious-free dynamic range -83 -75 sinad signal to noise + distortion single ended or pseudo differential mode 68 72 db snr signal-to-noise ratio 69 72.5 thd total harmonic distortion -81 -73 sfdr spurious-free dynamic range -83 -75 imd intermodulation distortion second order terms -75 db third order terms -100 channel-to-channel isolation -90 sample and hold aperture delay 13 ns aperture jitter 30 ps aperture delay matching 200 ps full power bandwidth 3 db, v dd = 5v 39 mhz 3 db, v dd = 3v 35 0.1 db, v dd = 5v 3.1 mhz 0.1 db, v dd = 3v 2.9 dc accuracy resolution 12 bits integral nonlinearity fully differential mode 0.4 0.99 lsb single-ended and pseudo differential modes 0.4 0.99 differential nonlinearity differential mode 0.25 0.99 lsb single-ended and pseudo differential modes 0.25 0.99 straight binary output coding offset error single-ended and pseudo- differential mode 0.5 6 lsb offset error match 0.5 gain error 0.75 2.5 lsb gain error match 0.5
www.austriamicrosystems.com revision 1.01 7 - 34 as1545 datasheet - electrical characteristics twos complement output coding positive gain error fully differential mode 2 lsb positive gain error match 0.5 zero code error 0.5 5 lsb zero code error match 0.5 negative gain error 2 lsb negative gain error match 0.5 analog input v inx single ended input voltage ranges bit range = 0 0 v ref v bit range = 1 0 2xv ref v inx - v iny pseudo differential input voltage ranges bit range = 0 v cm v cm +v ref v bit range = 1 v cm v cm + 2xv ref v inx & v iny differential input voltage ranges bit range = 0 v cm - v ref /2 v cm + v ref /2 v bit range = 1 v cm - v ref v cm + v ref v cm common mode voltage 0 v dd v leakage current 1 a absolute analog input voltage 0 v dd v input capacitance track mode 15 pf hold mode 8 pf reference input/output refin input voltage range 1 v dd v refout output reference voltage 2.475 2.5 2.525 v i leak leakage current 1 a input capacitance 30 pf refa, refb output impedance 5 refout tempco reference temperature coefficient 30 ppm/oc logic inputs v ih input high voltage v dd < 5v 0.7x v drive v v dd > 5v 2.8 v il input low voltage 0.4 v i in input current v in = 0 v or v drive -1 +1 a c in input capacitance 5 pf logic outputs v oh output high voltage i source = 200a v drive - 0.2 v vol output low voltage i sink = 200a 0.4 v table 3. electrical characteristics (continued) symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 1.01 8 - 34 as1545 datasheet - electrical characteristics floating state leakage current d out = gnd or v dd 1 a floating state output capacitance 7pf output coding straight binary (single-ended & pseudo-differential) two?s complement (fully differential) conversion rate t conv conversion time exclusive of t acq 15t sclk t acq track/hold acquisition time full-scale step input; v dd = 5v 90 ns full-scale step input; v dd = 3v 110 throughput rate 1 msps power requirements v dd positive supply voltage av dd = dv dd 2.7 5.25 v v drive interface supply voltage 2.7 av dd / dv dd v i dda +i ddd normal mode (static) v dd = 5.25v, internal ref. on 4 5 ma operational, f s = 1 msps v dd = 5.25v, internal ref. on 6.5 7 ma v dd = 2.7v, internal ref. on 5.2 5.5 ma partial power-down mode v dd = 5.25v, internal ref. on, static 500 a full power-down mode 1 a p d operational, f s = 1 msps v dd = 5.25v, internal ref. on 36.75 mw partial power-down v dd = 5.25v, internal ref. on 2.6 mw full power-down 5.25 w table 3. electrical characteristics (continued) symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 1.01 9 - 34 as1545 datasheet - electrical characteristics timing characteristics av dd = dv dd = 2.7v to 5.25v, v drive = 2.7v to av dd /dv dd , internal/external reference = 2.5v, t a = -40 to +85c (unless otherwise specified). figure 3. timing diagram table 4. timing characteristics 1 1. based on simulation and characterised samples. parameter symbol conditions min typ max units master clock frequency f sclk 120mhz conversion time t convert t sclk = 1/f sclk 15 x t sclk ns f sclk = 20 mhz 750 quiet time t quiet minimum time between end of serial read and next falling edge of csn 30 ns csn fall to sclk fall setup time t css v il of csn to v il of sclk 10 ns csn fall to d out enable t csdoe v il of csn to corner of d out 15 ns sclk fall to d out valid 2 2. v il of sclk to v oh of d out (rising edge) / v ol of d out (falling edge) t dov v dd = 2.7v 40 ns v dd = 5.25v 10 sclk fall to d out hold 3 3. v il of sclk to v ol of d out (rising edge) / v oh of d out (falling edge) t doh v dd = 2.7v 10 ns v dd = 5.25v 5 sclk low pulse width t cl v il to v il of sclk 0.4 t sclk 0.6 t sclk sclk high pulse width t ch v ih to v ih of sclk 0.4 t sclk 0.6 t sclk csn rise to d out disable t csdod v ih of csn to corner of d out to tristate 20 ns csn minimum pulse width t cspw v ih to v ih of csn 30 ns sclk fall to d out disable t dod v ih of sclk to corner of d out to tristate 550ns 1 2 3 4 5 t ch 0 0 0db11 db10 db9 db2 db1 db0 three-state 3 leading zeroes three- state douta doutb sclk csn t css 14 b t cl t csdod t quiet t doh t dov t csdoe t cspw
www.austriamicrosystems.co m revision 1.01 10 - 34 as1545 datasheet - typical operating characteristics 7 typical operating characteristics v dd = 5.25v, v ref = 2.5v, f sclk = 20mhz (50% duty), f sample = 1msps, c ref = 4.7f, range = 0, sgl/diff = 1, t amb = +25oc (unless otherwise specified). figure 4. integral nonlinearity vs. digital output code ; figure 5. diff. nonlinearity vs. digital output code; -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code inl (lsb) . external reference -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . external reference figure 6. integral nonlinearity vs. digital output code ; figure 7. diff. nonlinearity vs. digital output code; -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code inl (lsb) . internal reference -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . internal reference figure 8. fft @ 50khz, external reference; figure 9. fft @ 50khz, internal reference; -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 0 100 200 300 400 500 input signal frequency (khz) fft (dbc) . f sample = 1msps n fft = 65536 snr=72.8db thd = -84.6db sfdr = 88.2db sinad = 72.5db -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 0 100 200 300 400 500 input signal frequency (khz) fft (dbc) . f sample = 1msps n fft = 65536 snr=72.2db thd = -84.7db sfdr = 87.9db sinad = 71.9db
www.austriamicrosystems.co m revision 1.01 11 - 34 as1545 datasheet - typical operating characteristics figure 10. supply current vs. sampling rate; figure 11. supply current vs. supply voltage; 0 1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 sampling rate (ksps) supply current (ma) . vdd=5v vdd=3v 0 1 2 3 4 5 6 7 8 9 10 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 supply voltage (v) supply current (ma) . 1m sps st at ic figure 12. supply current vs. temperature; figure 13. full power-down current vs. v in ; 0 1 2 3 4 5 6 7 8 9 10 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (ma) . vdd=5v, 1msps vdd=5v, static vdd=3v, 1m sps vdd=3v, static 0 1 2 3 4 5 6 7 8 9 10 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 supply voltage (v) full power-down current (na) . figure 14. full power-down current vs. temperature; figure 15. partitial powe r-down current vs. temp.; 0 2 4 6 8 10 12 14 16 18 20 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) full power-down current (na) . vdd=5v vdd=3v 370 390 410 430 450 470 490 510 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) part. power-down current (a) . vdd=5v vdd=3v
www.austriamicrosystems.co m revision 1.01 12 - 34 as1545 datasheet - typical operating characteristics figure 16. part. power-down vs. temperature; figur e 17. dynamic performance vs. supply voltage; 0 50 100 150 200 250 300 350 400 450 500 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 supply voltage (v) part. power-down current (a) . int. ref = off int. ref = on 60 65 70 75 80 85 90 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 supply voltage (v) dynamic performance (db) . sina d snr thd sfdr figure 18. gain & offset error vs. supply voltage; figure 19. sinad vs. input frequency, single-ended; -3 -2 -1 0 1 2 3 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 supply voltage (v) offset/gain error (lsb) . gain error of f set error 64 66 68 70 72 74 10 100 1000 input frequency (khz) sinad (db) . rin=1 0ohm rin=50ohm rin=1 00ohm rin=1 kohm figure 20. sinad vs. input frequency, single-ended; fi gure 21. sinad vs. input frequency, differential; 55 60 65 70 75 10 100 1000 input frequency (khz) sinad (db) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v 60 62 64 66 68 70 72 74 10 100 1000 input frequency (khz) sinad (db) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v
www.austriamicrosystems.co m revision 1.01 13 - 34 as1545 datasheet - typical operating characteristics figure 22. enob vs. referencevoltage; figure 23. thd vs. input frequency, single-ended; 11 11.2 11.4 11.6 11.8 12 11.522.533.544.55 reference voltage (v) enob (bit) . vdd=5v vdd=3v -90 -85 -80 -75 -70 -65 10 100 1000 input frequency (khz) thd (db) . rin=1 0ohm rin=50ohm rin=1 00ohm rin=1 kohm figure 24. thd vs. input frequency, single-ended; fi gure 25. thd vs input frequency, differential; -90 -85 -80 -75 -70 -65 -60 -55 -50 10 100 1000 input frequency (khz) thd (db) . vdd=2.7v vdd=3.6v vdd=4.5v vdd=5.25v -90 -85 -80 -75 -70 -65 -60 10 100 1000 input frequency (khz) thd (db) . vdd=2.7v vdd=3.6v vdd=4.5v vdd=5.25v figure 26. enob vs. input frequency, single-ended; figure 27. enob vs. input fr equency, differential ; 10 10.4 10.8 11.2 11.6 12 10 100 1000 input frequency (khz) enob (bit) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v 10 10.4 10.8 11.2 11.6 12 10 100 1000 input frequency (khz) enob (bit) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v
www.austriamicrosystems.co m revision 1.01 14 - 34 as1545 datasheet - typical operating characteristics figure 28. snr vs. input frequency, single-ended; figure 29. snr vs. input frequency, differential ; 55 60 65 70 75 10 100 1000 input frequency (khz) sinad (db) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v 60 62 64 66 68 70 72 74 10 100 1000 input frequency (khz) snr (db) . vdd=5.25v vdd=4.5v vdd=3.6v vdd=2.7v figure 30. inl/dnl vs. reference voltage , v dd = 3v; figure 31. inl/dnl vs. reference voltage, v dd = 5v; -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 11.522.53 reference voltage (v) inl/dnl (lsb) . inlmax inlmin dnlmax dnlmin -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1 1.5 2 2.5 3 3.5 4 4.5 5 reference voltage (v) inl/dnl (lsb) . inlmax inlmin dnlmax dnlmin
www.austriamicrosystems.co m revision 1.01 15 - 34 as1545 datasheet - terminology 8 terminology acquisition time the acquisition time is the time needed by the adc to accura tely acquire the analog input voltage in the internal sampling capacitor. during this time the adc is in track mode. conversion time the conversion time is the time that the adc needs to c onvert an acquired analog input into a corresponding digital code. a successive approximation register adc usually needs a number of clocks dependant on the resolution. during this time the adc is in hold mode. throughput / sample rate the throughput or sample rate is the number of conversions performed by an adc per second. it is usually specified in samples per second (sps). th e throughput or sample rate is the reciprocal of the sum of acquisition time and conversion time. aperture delay the aperture delay defines the time between the falling ed ge of csn and the actual sampling instant. the aperture delay matching defines the maximum deviation of aperture delays across all 6 channels of one adc. aperture jitter the aperture jitter is the deviation of the actual sampling instant. this deviation is totally random and the standard deviation of the distribution is calculated with one sigma. differential nonlinearity (dnl) the differential nonlinearity is the deviation between the actu al code widths to the ideal code widths of 1 lsb, comparing all contiguous codes in the adc. the adc is specified according to its maximum and minimum dnl values across all codes. a dnl value equal to -1 indicates a missing code in the transfer function. integral nonlinearity (inl) the integral nonlinearity measures the deviation from the actual transfer func tion to the best straight line that minimizes the inl worst case values. offset error the offset error defines the absolute deviation of the firs t code transition (0x000h) to (0x001h) from the ideal input voltage (agnd + 0.5 lsb) in single ended and ps eudo differential mode (binary output coding). offset error = offset error match the offset error match defines the maximum deviation of the offset errors across all 6 channels of v in in single ended and pseudo differential mode (binary output coding). gain error the gain error defines the absolute deviation of the last c ode transition (0xffeh) to (0xfffh) from the ideal input voltage (v ref ? 1.5 lsb) in single ended and pseudo differ ential mode. the offset error is compensated. gain error = gain error match the gain error match defines the maximum deviation of the gain errors across all 6 channels of v in in single ended and pseudo differential mode (binary output coding). vin vref --------------- 4096 avg measuredcodes () ? offseterror avg measuredcodes () vin vref --------------- 4096 ? ?
www.austriamicrosystems.co m revision 1.01 16 - 34 as1545 datasheet - terminology zero code error the zero code error is the deviation of the midscale tran sition (all 0xfffh to all 0x000h in 2?s complement output coding) from the ideal input voltage (v in + - v in - = 0v) in fully differential mode. zero code error = zero code error match the zero code error match defines the maximum deviation of the zero code errors across all 6 channels of v in in fully differential mode (2?s complement output coding). positive gain error the positive gain error is the deviation last code transit ion (0x7feh) to (0x7ffh) in 2?s complement output coding from the ideal input voltage (v in + - v in - = +v ref - 0.5lsb @ range=1 and +v ref /2 - 0.5lsb @ range=0) in fully differential mode. positive gain error =zero code error ? negative gain error the negative gain error is the deviation first code transition (0x800h) to (0xfff h) in 2?s complement output coding from the ideal input voltage (v in + - v in - = -v ref + 0.5lsb @ range=1 and -v ref /2 + 0.5lsb @ range=0) in fully differential mode. negative gain error = positive / negative gain error match the positive / negative gain error match defines the maximu m deviation of the positive / negative gain errors across all 6 channels of v in in fully differential mode (2?s complement output coding). signal-to-noise plus distortion (sinad) the signal to noise plus distortion ratio defines the rati o between the rms value of t he fundamental (input signal) and the equivalent rms value of all other spectral co mponents below one-half the sampling frequency, including harmonics but excluding dc. sinad will be equ al to snr in an distortion free adc. effective number of bits (enob) the effective number of bits indicates the actual resolution of the converter. the enob can be calculated from the signal to noise plus distortion ratio (sinad). enob = signal-to-noise ratio (snr) the signal to noise ratio defines the ratio between the rms value of the fundamental (input signal) to the rms value of the sum of all other spectral components below one-hal f of the sampling frequency, excluding harmonics and dc. the theoretical snr for an ideal n bit adc is limited by the quantization error and is described by the formula: snr = 6.02*n +1.76 (db) therefore, for a 12-bit adc, the maximum snr is 74db. vinp vinn ? vref ---------------------------------- - 4096 2048 + avg measuredcodes () ? vinp vinn ? vref ---------------------------------- - 4096 2048 + avg measuredcodes () ? ?? ?? ?? vinp vinn ? vref ---------------------------------- - 4096 2048 + avg measuredcodes () ? ?? ?? ?? zerocodeerror ? sinad 1,76 ? 6,02 ----------------------------------
www.austriamicrosystems.co m revision 1.01 17 - 34 as1545 datasheet - terminology total harmonic distortion (thd) the total harmonic distortion is the ratio between the rms valu e of the fundamental (input signal) to the rms value of the first five harmonics. thd(dbc) = 20*log where: v1 is the rms power of the input frequency (fundamental) v2 to v6 are the rms values of the first five harmonics spurious free dynamic range (sfdr) the spurious free dynamic range defines the ratio between the rms value of the fundamental to the rms value of the largest peak off all spectral components below on e-half of the sampling frequency, including harmonics but excluding dc. channel to chan nel isolation the channel to channel isolation (crosstalk) defines the coupl ing of energy from one channel into the other channel in the adc. it is measured by applying a 40khz sine wave to all unselected channels and the attenuation to a 50khz input sine wave is determined. intermodulation distortion (imd) the intermodulation distortion measures the creations of additional spectral components that are caused by nonlinearities when applying a two tone sine wave on the inpu t of the adc. imd is the ration of the rms power in either the second or the third intermodulation pr oducts to the sum of both input frequencies. 2 nd order intermodulation produc ts (im2): f1+f2, f2-f1 3 rd order intermodulation products (im3): 2*f1-f2, 2*f2-f1, 2*f1+f2, 2*f2+f1 full power bandwidth / full linear bandwidth the full power bandwidth defines the frequency at which the reconstructed input signal amplitude drops 3db from the actual amplitude of the input signal, when applying a full scale signal. the full linear bandwidth defines the frequency at which th e reconstructed input signal amplitude drops 0.1db from the actual amplitude of the input signal, when applying a full scale signal. v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ++++ v 1 ----------------------------------------------------------------------- -
www.austriamicrosystems.co m revision 1.01 18 - 34 as1545 datasheet - detailed description 9 detailed description the as1545 is a dual, 6-channel (six single-ended, three pseudo-differential or three fully-differential for each multiplexer), 12-bit, 1 msps, high spee d, successive approximat ion (sar) analog-to-digi tal converter (adc). the as1545 is designed to operate with a single +2.7v to +5.25v supply and a sampling rate of up to 1 msps. the serial interface provides easy inte rfacing to microprocessors. the as1545 feature two on-chip, differential track-and-hol d amplifiers, two successive approximation adcs, and a serial interface with two separate data output pins on a single die. the as1545 is available in a 32-lead tqfn package, offering the user cons iderable space-saving advantage. the as1545 can convert analog input signals in the range [0v to v refin ] or [0v to 2 x v refin ] in single-ended or pseudo-differential mode or [-v refin /2 to +v refin /2] or [-v refin to +v refin ] in fully differential mode. the as1545 has an on-chip 2.5v reference that can be overdriven when an exter nal reference is preferred. if the internal reference is to be used then the output needs to be buffered first. the as1545 also features power-down options to allow power saving between conversions. the power-down feature is implemented via the standard serial interface. analog input the as1545 consists of successive approximation adcs, each around two capacitive dacs and 12 analog inputs. each on-board adc has six analog inputs that can be configured as six single-ended channels, three pseudo differential channels, or three fully differential channels. figure 32 and figure 33 shows one of these adcs in acquisition and conversion phase, respecti vely. the adc consists of a control logic, a sar, and two capacitive dacs. figure 32. adc acquisition acquisition time during data acquisition time (t acq ) sw3 is closed, sw1 and sw2 are in track position, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire th e differential signal on the input. at the raising edge of the csn signal, sw3 opens and sw1 and sw2 go into hold position, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the char ge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the ain+ and ain- pins must be matched. otherwise, the two inputs will have different settling times, resulting in errors. figure 33. adc conversion phase c s c s sw1 sw2 + - comparator capacitive dac capacitive dac control logic a a b b sw3 vref ain+ ain- ch0 ch1 ch2 ch3 ch4 ch5 c switch includes all parasitics analog input multiplexer r in r in 11pf 11pf c s c s sw1 sw2 + - comparator capacitive dac capacitive dac control logic a a b b sw3 vref ain+ ain- ch0 ch1 ch2 ch3 ch4 ch5 c switch includes all parasitics analog input multiplexer r in r in 11pf 11pf
www.austriamicrosystems.co m revision 1.01 19 - 34 as1545 datasheet - detailed description figure 34. typical application analog input composition the equivalent circuit of analog input struct ure of the as1545 in differential/pseu do differential modes is shown in the figure 35 . in single-ended mode, ain- is internally tied to agnd. the four diodes provide esd protection for the analog inputs. these diodes can conduct up to 10ma without causing irreversible damage to the part. note: make sure that the analog input signals never exceed the supply rails by more than 300mv. this causes the diodes to become forward-biased and starts conducting into the substrate. the c1 capacitors in figure 35 are of 4pf and can be attributed to pin capa citance. the value of these resistors is typically about 100 . the c2 capacitors are the adc?s sampling capa citors with a capacitance of 20pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the relevant analog input pins with optimum values of 10 and 10nf. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances signif icantly affect the ac performance of the adc and may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of t he particular application. figure 35. equivalent analog input circuit when no amplifier is used to drive th e analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated. the thd increases as the source impedance increases and performance degrades. figure 23 on page 13 shows a graph of the thd vs. the analog input signal frequency for various supplies in single- ended mode, while figure 25 shows the thd vs. the analog input signal frequency for various supplies in differential mode. figure 22 on page 13 shows a graph of the thd vs. the analog input frequency for different source impedances. ain 0 ain 1 refa avdd dvdd sclk csn range douta sgl/diff doutb refb refsel 100nf 1f 10f 100nf 1f 10f c + - 4.7f 4.7f 10nf 10nf 10 10 as1545 bin 0 bin 1 + - 10nf 10nf 10 10 a0 a1 a2 vdrive 1f 100nf vdd d d c1 ain+ c2 r1 vdd d d c1 c2 r1 ain- open for conversion, closed for tracking. open for conversion, closed for tracking. 4pf 4pf
www.austriamicrosystems.co m revision 1.01 20 - 34 as1545 datasheet - detailed description analog input modes table 5. address map address map sgl/ diff a2 a1 a0 adc a adc b comments ain + ain - bin + bin - 1 0 0 0 ain0 gnd bin0 gnd single ended 1 0 0 1 ain1 gnd bin1 gnd single ended 1 0 1 0 ain2 gnd bin2 gnd single ended 1 0 1 1 ain3 gnd bin3 gnd single ended 1 1 0 0 ain4 gnd bin4 gnd single ended 1 1 0 1 ain5 gnd bin5 gnd single ended 0 0 0 0 ain0 ain1 bin0 bin1 fully differential 0 0 0 1 ain0 ain1 bin0 bin1 pseudo differential 0 0 1 0 ain2 ain3 bin2 bin3 fully differential 0 0 1 1 ain2 ain3 bin2 bin3 pseudo differential 0 1 0 0 ain4 ain5 bin4 bin5 fully differential 0 1 0 1 ain4 ain5 bin4 bin5 pseudo differential 0 1 1 0 ain0 ain1 bin0 bin1 pseudo differential difference ? a/b phases ? counter table 6. input range sgl/diff range ain+ - ain- range coding example 1 0 0 to v ref straight ain+ - ain- = 1.766 v output decimal = 2894 output binary = 1011 0100 1110 1 1 0 to 2v ref straight ain+ - ain- = 1.766v output decimal = 1447 output binary = 0101 1010 0111 0 0 0 to v ref straight ain+ - ain- = 1.666 v output decimal = 2703 output binary = 1010 1010 1010 0 1 0 to 2v ref straight ain+ - ain- = 1.666 v output decimal = 1365 output binary = 0101 0101 0101 00-v ref /2 to +v ref /2 2?s comp ain+ - ain- = 1.666 v output decimal = 4095 output binary = 0111 1111 1111 (its 2?s comp) 01-v ref to +v ref 2?s comp ain+ - ain- = 1.666 v output decimal= 3413 output binary= 0101 0101 0101 (its 2?s comp)
www.austriamicrosystems.co m revision 1.01 21 - 34 as1545 datasheet - detailed description single-ended mode the as1545 consists of 12 single-ended analog input channel s with range that can be programmed to be either 0 to v ref or 0 to 2 v ref . note: in applications where the signal source has high imp edance, it is recommended to buffer the analog input before applying it to the adc. if the sampling analog input is bipolar, the internal reference of the adc can be used to externally bias up this signal to make it correctly formatted for the adc. figure 36 shows the connecting diagram when operating the adc in single- ended mode. figure 36. single-ended mode connection diagram figure 37. definition of single-ended input fully differential mode the as1545 consists of six differential analog input pairs. figure 38 defines the fully differential analog input of the as1545. the amplitude of the differential signal is the differ ence between the signals applied to the ain+ and ain- pins in each differential pair (ain+ - ain-). these pins should be simultaneously driven by two signals each of amplitude v ref /2 (or v ref , depending on the range required) that are 180o ou t of phase. if range = 1 is selected the amplitude of the differential signal is v ref regardless of the common mode (cm). the common mode is the average of the two signals and is therefore the volt age on which the two inputs are centered. (v in + + v in -)/2 (eq 1) althought fully differential oper ation with phase between inputs of 180 is recommanded, non true differential signals can also be applied. note: it is important to note that the absolute voltage of the analog inputs goes from agnd to v dd . + - + - v in r 3r r r refa/ refb ain0 to bin5 -1.25v 0v +1.25v 0v +2.5v 10nf 4.7f 10 0 < ain < vdd range = 0 0 < ain < vdd range = 1 vin vin tt vref 2vref
www.austriamicrosystems.co m revision 1.01 22 - 34 as1545 datasheet - detailed description figure 38. definition of fully differential input pseudo differential mode the as1545 consists of six pseudo differential pairs. in pseudo differential mode, ain+ is connected to the signal source with an amplitude of v ref or 2 v ref (depending on the range selected) to make use of the full dynamic range of the part. a dc input is applied to th e ain- pin. the voltage applied to this in put provides an offset from ground or a pseudo ground for the ain+ input. the benefit of pseudo differ ential inputs is that they separate the analog input signal ground from the adc?s ground allowing dc common-mode voltages to be cancelled. figure 39 shows a connection diagram for pseudo differential mode. figure 39. pseudo differential mode connection diagram figure 40. definition of pseudo differential input vcm ain+ ain- vref/2 0 < vcm < vdd 0 < ain-, ain+ < vdd vcm ain+ ain- vref 0 < vcm < vdd 0 < ain-, ain+ < vdd range = 0 range = 1 vin vin tt + - vin+ 4.7f dc input voltage vin- refa/ refb as1545 vref p-p ain- + vref ain+ ain- 0 < ain-, ain+ < vdd 0 < ain-, ain+ < vdd range = 0 range = 1 ain- + 2vref ain+ ain- vref vin vin tt 2vref
www.austriamicrosystems.co m revision 1.01 23 - 34 as1545 datasheet - detailed description analog-to-digital conversion the analog inputs of the as1545 can be configured as single -ended pseudo-differential or fully differential via the sgl/ diff logic pin, as shown in figure 41 . if this pin is coupled to a logic low, the analog input channels to each on-chip adc are set up as three fully differential pairs or 3 pseudo-diff erential inputs. if this pin is at logic high, the analog inpu t channels to each on-chip adc are set up as six single-ended analog inputs. the required logic level on this pin needs to be established prior to the acquisition time and remain unchanged during the conversion time until the track-and- hold has returned to track. the track-and-hold returns to track on the 13th rising edge of sclk after the csn falling edge (see figure 51) . if the level on this pin is changed, it is recogniz ed by the as1545; therefor e, keep the same logic level during acquisition and conversion to avoid corrupting the conversion in progress. the channels used for simultaneous conversions are selected via the multiplexer address input pins, a0 to a2. the logic states of these pins also need to be established prio r to the acquisition time; however, they may change during the conversion time, provided that the mode is not changed. if the mode is change d from fully differential to pseudo- differential, for example, then the acquisition time would st art again from this point. the selected input channels are decoded as shown in table 5 on page 20 . the analog input range of the as1545 can be selected as [0v to v ref or -v ref /2 to +v ref /2] or [0v to 2v ref or -v ref to +v ref ] via the range and mode pin (see table 5 on page 20) . this selection is made in a similar fashion to that of the sgl/diff pin by setting t he logic state of the range pin a time t acq prior to the falling edge of csn. the logic level on this pin can be altered after the third falling edg e of sclk. if this pin is tied to a logic low, the analog inp ut range selected is [0v to v ref or -v ref /2 to +v ref /2]. if this pin is tied to a logic high, the analog input range selected is [0v to 2v ref or -v ref to +v ref ]. figure 41. selecting differentia l or singe-ended configuration output coding the as1545 output coding is set to either twos complem ent or straight binary, depending on which analog input configuration is selected for a conver sion. output coding scheme for each possibl e analog input conf iguration is show in the ta b l e 7 . transfer functions the designed code transitions occur at successive integer lsb values (1 lsb, 2 lsb, and so on). in single-ended mode, the lsb size is v ref /4096 when the 0v to v ref range is used, and the lsb size is 2 v ref /4096 when the 0v to 2 v ref range is used. in differential mode, the lsb size is 2 v ref /4096 when the 0v to v ref . the ideal transfer characteristic for the as1545 when straight bi nary coding is output is shown (with the 2 v ref range) in figure 42 & figure 43 on page 24 , and figure 44 & figure 45 on page 24 shows the twos complement. table 7. as1545 output coding mode output coding differential twos complement single-ended straight binary pseudo-differential straight binary csn sclk sgl/ diff t acq a b 14 1 1 14
www.austriamicrosystems.co m revision 1.01 24 - 34 as1545 datasheet - detailed description figure 42. straight binary transfer function for figure 43. straight binary transfer function for single-ended, range = 0 single-ended, range = 1 figure 44. two?s complement transfer function for figure 45. two?s complement transfer function for differential, range = 0 differential, range = 1 digital inputs v drive functionality the as1545 also has a v drive feature to control the voltage at which the serial interface operates and allows the adc to easily interface to both 3v and 5v processors . for example, if the as1545 was operated with a v dd of 5v, the v drive pin could be powered from a 3v supply, allowing a large dynamic range with low voltage digital processors. therefore, the as1545 could be used with the 2 v ref input range, with a v dd of 5v while still being able to interface to 3v digital parts. 11...111 11...110 11....101 00...011 00...010 00...001 00...000 11...111 11...110 11....101 00...011 00...010 00...001 00...000 output code 0123 input voltage v inx (lsb) fs - 3/2lsb full scale = v ref zero scale = 0 1lsb = v ref /4096 output code 0 1 2 3 input voltage v inx - v iny (lsb) fs - 3/2lsb full scale (fs) transition full scale = +2v ref zero scale = 0 1lsb = v ref /4096 full scale (fs) transition 011....111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 output code -fs zs input voltage v inx (lsb) +fs - 1lsb 011....111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 output code -fs zs input voltage v inx - v iny (lsb) +fs - 1lsb full scale = v ref /2 zero scale = -v ref /2 1lsb = v ref /4096 full scale = +v ref zero scale = -v ref 1lsb = v ref /4096
www.austriamicrosystems.co m revision 1.01 25 - 34 as1545 datasheet - application information 10 application information operation modes the operation mode of the as1545 is selected by controlling the (logic) state of the csn signal during a conversion process. there are three possible modes of operation: full power-up mode, full po wer-down mode, and partial power-down mode. after a conversion is initiated, the point at which csn is pulled high determines which power-down mode, if any, the device enters. similarly, in power-down mode, csn can control whether the device returns to full power-up mode or remains in power-down. these modes of operation provides flexible power management and can be selected to optimize the power dissipation/throughp ut rate ratio for differing application requirements. full power-up mode in this mode the as1545 is fully powered all the time without any power-up time. this mode is suitable for applications that need the fastest throughput rates. figure 46 shows the general diagram of the operation of the as1545 in this mode. on the falling edge of csn conversion is initiated. to ensure that the part remains fully powered up at all times, csn must remain low until at least 10 sclk falling edge s have elapsed after the falling edge of csn. the conversion is terminated and d out a and d out b go back into three-state, if csn is brought high any time after the 10th sclk falling edge but before the 15th sc lk falling edge. during this process the part remains powered up. figure 46. full power-up mode operation fiveteen serial clock cycles are required to complete the conversion and access the conversion result. the d out line does not return to three-state after 15 sclk cycles have elapsed, but instead does so when csn is brought high again. if csn is left low for another sclk cycle (for example, if only a 16 sclk burst is available), one trailing zeros are clocked out after the data. if csn is left low for a furthe r 16 sclk cycles, the result from the other adc on board is also accessed on the same d out line, as shown in figure 52 (see serial interface on page 28) once 32 sclk cycles have elapsed, the d out line returns to three-state on the 32nd sclk falling edge. if csn is brought high prior to this, the d out line returns to three-state at that point. once a data transfer is complete and d out a and d out b have returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing csn low again (assuming the required acquisition time is allowed). full power-down mode this mode is intended for applications where throughput ra tes are slower. in this mode the as1545 will stay power down until the falling edge of csn. the device continues to power-up when the csn is held low till the falling edge of the 10th sclk. when the as1545 is in full power-down, all analog circuitr y is powered down. full power-down is entered in a similar way as partial power-down, except the timing sequence shown in figure 50 must be executed twice. the conversion process must be interrupted in a similar fashion by bringing csn high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk. the device enters partial power-down at this point. to reach full power- down, the next conversion cycl e must be interrupted in the same way, as shown in figure 48 . once csn is brought high in this window of sclks, the part completely powers down. note: it is important to note, that the full power-down mode can only be es tablished if both digital outputs, d out a and d out b are not left floating. therefore a pulldown or pullup of >1g is required. 3 leading zeros + conversion result 12bits 1 15 10 d out a d out b sclk csn
www.austriamicrosystems.co m revision 1.01 26 - 34 as1545 datasheet - application information figure 47. exiting partial power-down mode figure 48. entering full power-down mode figure 49. exiting full power-down mode note: it is not necessary to complete the 15 sclks onc e csn is brought high to enter a power-down mode. the required power-up time must elapse before a conversion can be initiated, as shown in figure 49 . partial power-down mode this mode is intended for use in applications where slower throughput rates are required. either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the as1545 is in partial power-down, all analog circuitry is powered down except for the on-chip refe rence and reference buffer. 1 15 d out a d out b sclk csn 10 invalid data valid data 1 15 the part begins to power-up the part is fully powered-up t power-up1 1 15 d out a d out b sclk csn 10 invalid data the part enters partial power down the part enters fully powered down 1 15 10 the part begins to power-up invalid data three-state three-state 2 2 1 15 d out a d out b sclk csn 10 invalid data valid data 1 15 the part begins to power-up the part is fully powered-up t power-up1
www.austriamicrosystems.co m revision 1.01 27 - 34 as1545 datasheet - application information to enter partial power-down mode, the conversion process must be interrupted by bringing csn high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk, as shown in figure 50 . once csn is brought high in this window of sclks, the part enters pa rtial power-down, the conversion that was initiated by the falling edge of csn is terminated, and d out a and d out b go back into three-state. if csn is brought high before the second sclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power- down due to glitches on the csn line. figure 50. partial power-down mode to exit this mode of operation and power up the as1545 aga in, a dummy conversion is performed. on the falling edge of csn, the device begins to power up and continues to powe r up as long as csn is held low until after the falling edge of the 10th sclk. the device is fully powered up after approxima tely 1 s has elapsed, and valid data results from the next conversion, as shown in figure 47 . if csn is brought high before the second falling edge of sclk, the as1545 again goes into partial power-down. this avoids acciden tal power-up due to glitches on the csn line. although the device may begin to power up on the falling edge of csn, it powers down again on the rising edge of csn. if the as1545 is already in partial power-down mode and csn is br ought high between the second and 10th falling edges of sclk, the device enters full power-down mode. power-up times as described in detail, the as1545 has two power-down modes, partial power-down and full power-down. this section deals with the power-up time required when coming out of eit her of these modes. it shou ld be noted that the power-up times, as explained in this section, apply with the recommended capacitors in place on the d cap a and d cap b pins. the power-up time is always 1s, independent of the mode currently in. note: it is important to note that, when using the internal re ference, charging the external reference capacitance typ - ically needs around 250s but can take up to 1ms. when power supplies are first applied to the as1545, the a dc may power up in either of the power-down modes or normal mode. because of this, it is best to allow a dummy c ycle to elapse to ensure the part is fully powered up before attempting a valid conversion. likewise, if it is intended to keep the part in the partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. t he first dummy cycle must hold csn low until after the 10th sclk falling edge (see figure 46) ; in the second cycle, csn must be br ought high before the 10th sclk edge but after the second sclk falling edge (see figure 50) . alternatively, if it is inten ded to place the part in full power-down mode when the supplies are applied, then three du mmy cycles must be initiated. the first dummy cycle must hold csn low until after the 10th sclk falling edge (see figure 46) ; the second and third dummy cycles place the part in full power-down (see figure 48) . once supplies are applied to the as1545, enough time must be allowed for any external reference to power up and charge the various reference buffer decoupling capacitors to their final values. 1 15 10 d out a d out b sclk csn 2 three-state
www.austriamicrosystems.co m revision 1.01 28 - 34 as1545 datasheet - application information power vs. throughput rate the power consumption of the as1545 varies with throughput rate. when using very slow throughput rates and as fast an sclk frequency as possible, the various power-down op tions can be used to make significant power savings. however, the as1545 quiescent current is low enough that even without using the powe r-down options, there is a noticeable variation in power consumption with sampling rate. this is true whether a fixed sclk value is used or if it is scaled with the sampling rate. figure 10 on page 11 shows plots of power vs. the throughput rate when operating in normal mode for a fixed maximum sclk frequency, and an sclk frequency that scales with the sampling rate with v dd = 3v and v dd = 5v, respectively. in all cases, the internal reference was used. serial interface the timing diagram for serial interfacing to the as1545 is shown in figure 51 . the serial clock provides the conversion clock and controls the transfer of info rmation from the as1545 during conversion. the csn signal initiates the data transfer and conversion pr ocess. the falling edge of csn puts the track-and-hold into hold mode, at which point the analog input is sample d and the bus is taken out of th ree-state. the conversion is also initiated at this point and requires a minimum of 15 sclks to complete. once 13 sclk falling edges have elapsed, the track-and-hold goes back into tr ack on the next sclk rising edge, as shown in figure 51 at point b. if a 16-sclk transfer is used, then two trailing zeros will appear after the final lsb. on the rising edge of csn, the conversion is terminated and d out a and d out b go back into three-state. if csn is not brought high but is instead held low for a further 15 sclk cycles on d out a, the data from conversion b is output on d out a (followed by 1 trailing zero). likewise, if csn is held low fo r a further 15 sclk cycles on d out b, the data from conversion a is output on d out b. this is illustrated in figure 52 where the case for d out a is shown. in this case, the d out line in use goes back into three-state on the 32nd sclk falling edge or t he rising edge of csn, whichever occurs first. a minimum of 15 serial clock cycles are required to pe rform the conversion process and to access data from one conversion on either data line of the as1545. csn going low provides the 3 leading zeros to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges. therefore, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. the 12-bit result then follows after a third leading zero with the final bit in the data transfer valid on the 15th falling edge, having being clocked out on the previous (14th) falling edge. it may also be possible to read in data on each sclk rising edge depending on the sclk frequency or the supply voltage. the secondrising edge of sclk after the csn falling edge would have the third leading zero provided, and the 14th rising sclk edge would have db0 provided. if a falling edge of sclk is coincident with the falling edge of csn, then this falling edge of sclk is not acknowledged by the as1545, and the next falling edge of sclk will be the first registered after the falling edge of csn. figure 51. timing diagram 1 2 3 4 5 t ch 0 0 0db11 db10 db9 db2 db1 db0 three-state 3 leading zeroes three- state douta doutb sclk csn t css 14 b t cl t csdod t quiet t doh t dov t csdoe t cspw
www.austriamicrosystems.co m revision 1.01 29 - 34 as1545 datasheet - application information figure 52. reading data from both adcs on one d out line with 32 sclks figure 53. 32 sclks data transfer for all modes in d outa , d outb difference calculator and quadrature signals calculator the as1545 internally calculates the difference between the output codes of adc a and adc b. there are several requirements that need to be taken into a ccount in order to work with the differen ce calculator. first off, the output data of both adcs needs to be in straight binary coding. this means that the difference calculator will only give the correct results in single ended and pseudo differential modes. also, it is important to note that in order to read the data from the difference calculator we must read all 32 bits of data of the adc, therefore reducing th e overall sampling rate of the adc by half. the difference calculator will always give you a 13 bit two?s complement result. the first bit is the sign of the operation and the next 12 bits are the data. for simplicity in the de sign, an systematic error of 1 lsb can be expected from the difference calculator. below we have an detailed example describing the operation of the difference calculator. let?s assume that v in a = 1.667v v in b = 2v v ref = 2.5v and we are working in single ended mode. dout_a = 1010 1010 1010 or 2730 in decimal dout_b = 1100 1100 1100 or 3276 in decimal the difference should be 2730-3276=-546 in decimal in 2?s complement -546 is 1 1101 1101 1110 in binary. this is a 1 for the minus sign plus 4096-546=3550 in decimal which corresponds to 1101 1101 1110 in binary as stated before, there is a -1lsb error in the operati on so the actual output should be -547 in decimal which corresponds to 1 1101 1101 1101 in binary which is the result that the difference calculator clocks out. 1 2 3 4 5 t ch 0 0 0 db11 a db10 a 0 0 0 three- state 3 leading zeroes three- state douta sclk csn t css 18 t cl t doh t csdoe 32 15 16 17 0 db11 b db0 b 0 t dod 1 trailing zero 3 leading zeroes 1 trailing zero t dov 000 sdata_a 00 0+sdata_b 0 000 sdata_a counter + dir + a + b 0 000 sdata_a dif 0 douta csn douta* doutb * only applicable when sgl/diff = 0 ; 2 =1, 1 = 1 , 0 = 0 0 00 0 00 0 16bit 16bit
www.austriamicrosystems.co m revision 1.01 30 - 34 as1545 datasheet - application information on top of the difference calculator, the adc also provide us with information regarding i nput signals in quadrature (90 degrees phase difference) li ke the ones we would get from a positio n calculation system of a motor control. in order for this mode to work, we mu st have sgl/diff=0, a2=1. a1=1. a0=0, ac cording to what is specified in the channel addresses table. also, it is important to note that in order to read the da ta from the quadrature inputs calculator we must read all 32 bits of data of the adc, th erefore reducing the overall samp ling rate of the adc by half. the adc provides us with the following information: - phase a and phase b bits, dividing the period into four quadrants - dir bit, which indicates the dire ction of the rotation of the rotor - counter, this is a 10 bit word that, in the case of using a step down in the rotor indicates the number of times the step down has spun. the counter increa ses twice per period if dir is equal zero and decreases twice per period if dir equals one. figure 54. a to b phase direction of the rotor based on the dir bit if the rotor is rotating as the abov e picture, the direction bit is low. if the rotor is rotating in the opposite directi on to the above picture, the direction bit is high. note: this mode works only for sgl/diff=0, a2=1. a1=1. a0=0. phase a phase b cos sinus direction = 0 direction = 1 code 2048 code 4095 code 0
www.austriamicrosystems.co m revision 1.01 31 - 34 as1545 datasheet - application hints 11 application hints grounding and layout the analog and digital supplies to the as1545 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. th e printed circuit board (pcb) that houses the as1545 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this design facilitates the use of ground planes that can be easily separated. to provide optimum shielding for ground planes, a minimum et ch technique is generally best. all three agnd pins of the as1545 should be sunk in the agnd plane. digital and analog ground planes should be joined in only one place. if the as1545 is in a system where multiple devices requir e an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the as1545. avoid running digital lines under the device as this couple s noise onto the die. however, the analog ground plane should be allowed to run under the as1545 to avoid noise coupling. the power supply lines to the as1545 should use as large a trace as possible to provide low impedance path s and reduce the effects of glitches on the power supply line. to avoid radiating noise to ot her sections of the board, fa st switching signals, such as clocks, should be shielded with digital ground, and clock signals should never run near th e analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. a microstrip technique is the best method but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f ceramic capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best result s from these decoupling components, they must be placed as close as possible to the device, ideally right up against t he device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance ( esi), such as the common ce ramic types or surface-mount types. these low esr and esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. pcb design guidelines for tqfn the lands on the tqfnpackage are rectangular. the pcb pa d for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width, thereby having a portion of the pad exposed. to ensure that the solder joint size is maximized, the land should be centered on the pad. the bottom of the chip scale package has a thermal pad. th e thermal pad on the pcb should be at least as large as the exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. to improve thermal performance of the pa ckage, use thermal via on the pcb inco rporating them in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. the user should connect the pcb thermal pad to agnd.
www.austriamicrosystems.co m revision 1.01 32 - 34 as1545 datasheet - package drawings and markings 12 package drawings and markings figure 55. 32-lead tqfn package notes: 1. figure 55 is shown for illustration only. 2. all dimensions are in millimeters; angles in degrees. 3. dimensioning and tolerancing conform to asme y14.5 m-1994 . 4. n is the total number of terminals. 5. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1, spp-012 . details of ter - minal #1 identifier are optional, but must be located within t he zone indicated. the terminal #1 identifier may be either a mold or marked feature. 6. dimension b applies to metallized terminal and is me asured between 0.15mm and 0.30mm from the terminal tip. 7. nd refers to the maximum number of terminals on side d. 8. unilateral coplanarity zone applies to the ex posed heat sink slug as well as the terminals table 8. 32-lead tqfn package dimensions symbol min nom max note symbol min nom max note a 0.70 0.75 0.80 1,2 b 0.18 0.25 0.30 1,2,5 a1 0.00 0.02 0.05 1,2 l 0.30 0.40 0.50 1,2,5 l1 0.03 0.15 1,2 n 32 1,2,5 k 0.20 1,2 nd 8 1,2,5 e0.5 ne 8 1,2,5 d2 3.30 3.45 3.55 1,2,5 aaa 0.10 1,2 e2 3.30 3.45 3.55 1,2,5 bbb 0.10 1,2 d bsc 5.00 1,2,5 ccc 0.10 1,2 e bsc 5.00 1,2,5 ddd 0.05 1,2 datum a or b even terminal side te rm i na l ti p e e/2 l1 -c- a3 a1 side view plane a ccc c 0.08 c seating d d/2 index area e aaa c aaa c top view 2x 2x (d/2 xe/2) e/2 -b- -a- e b d2/2 d2 e2/2 e2 bbb c a b ddd c -b- -a- nn-1 btm view (d/2 xe/2) index area see detail b see detail b
www.austriamicrosystems.co m revision 1.01 33 - 34 as1545 datasheet - ordering information 13 ordering information the device is available as the standard products shown in table 9 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.a ustriamicrosystems.com/distributor table 9. ordering information ordering code description marking delivery form package AS1545-BQFT dual, 12-bit, 1msps, sar adc as1545 t&r 32-lead tqfn
www.austriamicrosystems.co m revision 1.01 34 - 34 as1545 datasheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaet ten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environ mental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact

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